Performance Evaluation of Division Algorithms in FPGA

Abstract

One of the main reasons that researchers interact with the Field Programmable Gate Arrays (FPGAs) is the parallel processing feature which can be used to make high speed designs. However, arithmetic operations such as division and multiplication in FPGA limit this feature considerably. Although, hardware multipliers are included to reduce the effect, there are no built-in hardware division elements in any FPGA, where it is the most complicated and expensive operation among the others. This paper presents a comparative study of performance for several distributed division solutions for FPGAs. Restoring, Non-restoring, Radix-2 SRT (Sweeney, Robertson and Tocher), Radix-2 SRT with CSA (Carry Save Adder) and the Goldschmidt’s division algorithms were selected for the study. In addition, Xilinx’s LogiCORE Divider Generator core v3.0 and Matlab Simulink Divider Generator 3.0 were also evaluated. The comparison was done by means of resource utilization (RU), delay in critical path (DT) and area×time (RU×DT) parameter for Xilinx Spartan-3E XC3S100E and Spartan-6 XC6LX16 devices. The lowest logic consumption and RU×DT were seen in the non-restoring algorithmic divider in both Spartan-3E and Spartan-6. The lowest DT for Spartan-3E and Spartan-6 were reported by the Simulink Divider Generator 3.0, which is 3.692 ns and the Xilinx’s LogiCORE Divider Generator core v3.0, which is 2.626 ns respectively. However, the non-restoring divider is identified as the best balanced division solution by concerting the RU×DT parameter.